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ISL8012
Data Sheet March 11, 2008 FN6616.0
2A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator
The ISL8012 is a high efficiency, monolithic, synchronous step-down DC/DC converter that can deliver up to 2A continuous output current from a 2.7V to 5.5V input supply. It uses a current control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. The ISL8012 integrates a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 240mV dropout voltage at 2A output current. High 1MHz pulse-width modulation (PWM) switching frequency allows the use of small external components. The ISL8012 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference while discontinuous mode provides high efficiency by reducing switching losses at light loads. Fault protection is provided by internal current limiting during short circuit and overcurrent conditions, an output over voltage comparator and over-temperature monitor circuit. A power good output voltage monitor indicates when the output is in regulation. The ISL8012 offers a 1ms Power Good (PG) timer at power-up. When shutdown, ISL8012 discharges the output capacitor. Other features include internal soft-start, internal compensation, overcurrent protection, and thermal shutdown. The ISL8012 is offered in a space saving 3mmx3mm 10 Ld DFN package lead free package with exposed pad lead frames for low thermal. The complete converter occupies less than 0.35in2 area.
Features
* High Efficiency Synchronous Buck Regulator with up to 95% Efficiency * Power-Good (PG) Output with a 1ms Delay * 2.7V to 5.5V Supply Voltage * 3% Output Accuracy Over-Temperature/Load/Line * 2A Guaranteed Output Current * Start-up with Pre-Biased Output * Internal Soft-Start - 1ms * Soft-Stop Output Discharge During Disabled * 40A Quiescent Supply Current in PFM Mode * Selectable Forced PWM Mode and PFM Mode * Less than 1A Logic Controlled Shutdown Current * 100% Maximum Duty Cycle * Internal Current Mode Compensation * Peak Current Limiting and Hiccup Mode Short Circuit Protection * Over-Temperature Protection * Small 10 Ld 3mmx3mm DFN * Pb-Free (RoHS Compliant)
Applications
* DC/DC POL Modules * C/P, FPGA and DSP Power * Plug-in DC/DC Modules for Routers and Switchers * Portable Instruments * Test and Measurement Systems * Li-ion Battery Powered Devices * Small Form Factor (SFP) Modules * Bar Code Readers
Ordering Information
PART NUMBER (Note) ISL8012IRZ* TEMP. RANGE PART (C) MARKING 012Z PACKAGE (Pb-free) PKG. DWG. #
Pinout
ISL8012 (10 LD DFN) TOP VIEW
VIN VCC 1 2 10 LX 9 8 7 6 PGND SGND VFB RSI
-40 to +85 10 Ld 3x3 DFN L10.3x3C
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
EN 3 PG 4
MODE 5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL8012 Typical Application
L INPUT 2.7V TO 5.5V VIN LX C2 22F C1 22F PGND R2 124k C3* 220pF OUTPUT 1.8V/2A
ISL8012
EN R1 100k PG VFB SGND R3 100k
MODE
RSI
*C3 is optional
FIGURE 1. TYPICAL APPLICATION DIAGRAM
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ISL8012 Block Diagram
MODE
SOFT-START SHUTDOWN EN BANDGAP 0.8V
27pF 390k
SHUTDOWN
OSCILLATOR EAMP + COMP PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER
VIN
VFB SLOPE COMP CSA 0.864V + + OCP
0.736V + SKIP PG 1ms DELAY
RSI
0.2V
3
+ +
LX
+
GND
+
1V
0.25V
ZERO-CROSS SENSING
SCP +
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
FN6616.0 March 11, 2008
ISL8012
Absolute Maximum Ratings (Reference to GND)
VIN, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V EN, RSI, PG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V LX. . . . . . . . . . . . . . . . . . . . . . . . . .-1.5V (100ns)/-0.3V (DC) to 6.5V VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 10 Ld 3x3 DFN Package . . . . . . . . . 49 5.5 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. 3. Limits established by characterization and are not production tested. 4. Parts are 100% tested at +25C. Temperature limits established by characterization and are not production tested.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = -40C to +85C, VIN = 3.6V, EN = VCC, unless otherwise noted. Typical values are at TA = +25C. SYMBOL TEST CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITS
PARAMETER INPUT SUPPLY VIN Under Voltage Lockout Threshold
VUVLO
Rising Falling 2.2
2.5 2.4 40 15 6 0.1
2.7
V V
Quiescent Supply Current
IVIN
MODE = VIN, no load at the output MODE = VIN, no load at the output and no switches switching; design info only MODE = SGND, no load at the output
60
A A
8 2
mA A
Shut Down Supply Current OUTPUT REGULATION VFB Regulation Voltage VFB Bias Current Output Voltage Accuracy Line Regulation COMPENSATION Error Amplifier Trans-Conductance LX P-Channel MOSFET ON-Resistance
ISD
VIN = 5.5V, EN = low
VVFB IVFB
TA = 0C to +85C VFB = 0.75V VIN = VO + 0.5V to 5.5V, IO = 0A to 2A (Note 3) VIN = VO + 0.5V to 5.5V (minimal 2.7V), IOUT = 400mA
0.784
0.8 0.1
0.816
V A
-3 0.2
3
% %/V
Adjustable version, design info only
20
A/V
VIN = 5.5V, IO = 200mA VIN = 2.7V, IO = 200mA
0.12 0.21 0.11 0.13 2.65 3.00 100
0.22 0.27 0.22 0.27 3.50
A %
N-Channel MOSFET ON-Resistance
VIN = 5.5V, IO = 200mA VIN = 2.7V, IO = 200mA
P-Channel MOSFET Peak Current Limit LX Maximum Duty Cycle PWM Switching Frequency
IPK
fS
TA = 0C to +85C
0.840
1
1.16
MHz
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ISL8012
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = -40C to +85C, VIN = 3.6V, EN = VCC, unless otherwise noted. Typical values are at TA = +25C. (Continued) SYMBOL TEST CONDITIONS MODE = low (forced PWM mode) VIN = 3.6V MIN (Note 4) TYP 80 1.1 MAX (Note 4) 100 UNITS ns ms
PARAMETER LX Minimum On-Time Soft-Start-Up Time PG Output Low Voltage Delay Time PG Pin Leakage Current Minimum Supply Voltage for Valid PG Signal Internal PGOOD Low Rising Threshold Internal PGOOD Low Falling Threshold Internal PGOOD High Rising Threshold Internal PGOOD High Falling Threshold Internal PGOOD Delay Time EN, MODE, RSI Logic Input Low Logic Input High Logic Input Leakage Current
Sinking 1mA, VFB = 0.7V 1 PG = VIN = 3.6V 1.2 Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage 89 85 107 104 92 88 110 107 30 0.01
0.3
V ms
0.1
A V
95 91 113 110
% % % % s
0.4 1.4 Pulled up to 5.5V 0.1 1
V V A
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ISL8012 Pin Descriptions
VIN (Pin 1)
Input supply voltage. Connect a 10F ceramic capacitor to power ground.
VFB (Pin 7)
Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage (ISL8012-ADJ). For preset output voltage, connect this pin to the output.
VCC (Pin 2)
Input supply for the logic. Connect to VIN.
SGND (Pin 8)
System ground for the control logic. All voltage levels are measured with respect to this pin.
EN (Pin 3)
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating.
PGND (Pin 9)
Ground connect for the IC and thermal relief for the package. The exposed pad must be connected to PGND and soldered to the PCB.
PG (Pin 4)
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the output voltage. This output can be reset by a low RSI signal. 1ms starts when RSI goes to high.
LX (Pin 10)
Switching node connection. Connect to one terminal of inductor.
MODE (Pin 5)
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating.
Exposed Pad
The exposed pad must be connected to the PGND and SGND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance.
RSI (Pin 6)
This input resets the 1ms timer. When the output voltage is within the PGOOD window, an internal timer is started and generates a PG signal 1ms later when RSI is low. A high RSI resets PG and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition.
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ISL8012 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5H, C1 = 2x10F, C2 = 2x10F, IOUT = 0A to 2A).
100 90 EFFICIENCY (%) EFFICIENCY (%) 80 70 60 50 40 30 20 0.00 2.5VOUT 1.8VOUT 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 1.5VOUT 1.2VOUT 100 90 80 70 60 50 40 30 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.5VOUT 1.2VOUT 1.8VOUT 2.5VOUT
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
100 90 EFFICIENCY (%) EFFICIENCY (%) 80 70 60 50 40 30 20 0.00 3.3VOUT 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 1.5VOUT 1.2VOUT 1.8VOUT 2.5VOUT
100 90 80 70 60 50 40 30 20 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT LOAD (A) 0.7 0.8 1.5VOUT 1.8VOUT 1.2VOUT 2.5VOUT 3.3VOUT
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
1.000 POWER DISSIPATION (mW) POWER DISSIPATION (W) 0.875 0.750 0.625 0.500 0.375 0.250 0.125 0 0.00 0.25 0.50 0.75 1.00 1.25 5VIN PWM 5VIN PFM 3.3VIN PFM 1.50 1.75 2.00 3.3VIN PWM
160 140 120 100 80 60 40 20 0 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 PWM MODE
OUTPUT LOAD (A)
FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 8. POWER DISSIPATION WITH NO LOAD vs VIN (PWM VOUT = 1.8V)
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ISL8012 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5H, C1 = 2x10F, C2 = 2x10F, IOUT = 0A to 2A). (Continued)
0.50 POWER DISSIPATION (mW) 0.45 OUTPUT VOLTAGE (V) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 PFM 1.24 1.23 1.22 1.21 1.20 1.19 1.18 1.17 1.16 0.00 0.25 0.50 3.3VIN PFM 5VIN PFM 0.75 1.00 1.25 OUTPUT LOAD (A) 1.50 1.75 2.00 5VIN PWM 3.3VIN PWM
FIGURE 9. POWER DISSIPATION WITH NO LOAD vs VIN (PFM VOUT = 1.8V)
FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
1.55 1.54 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.53 1.52 1.51 1.50 1.49 1.48 1.47 0.00 0.25 3.3VIN PFM 5VIN PFM 0.75 1.00 1.25 1.50 1.75 2.00 5VIN PWM 3.3VIN PWM
1.83 1.82 1.81 1.80 1.79 1.78 1.77 1.76 1.75 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 3.3VIN PFM 5VIN PFM 5VIN PWM 3.3VIN PWM
0.50
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
2.59 2.57 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.55 2.53 2.51 2.49 2.47 2.45 2.43 0.00 5VIN PFM 3.3VIN PFM 3.3VIN PWM 5VIN PWM
3.36 3.35 3.34 3.33 3.32 3.31 3.30 3.29 0.75 1.00 1.25 1.50 1.75 2.00 3.28 0.00 4.5VIN PFM 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 5VIN PWM 5VIN PFM 4.5VIN PWM
0.25
0.50
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
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ISL8012 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5H, C1 = 2x10F, C2 = 2x10F, IOUT = 0A to 2A). (Continued)
LX 2V/DIV
LX 2V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV IL 0.5A/DIV FIGURE 15. STEADY STATE OPERATION AT NO LOAD (PWM), (1s/DIV) FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PFM), (1s/DIV)
LX 2V/DIV
LX 2V/DIV VOUT RIPPLE 50mV/DIV
IL 0.5A/DIV
VOUT RIPPLE 20mV/DIV
IL 0.5A/DIV FIGURE 18. MODE TRANSITION CCM TO DCM, (5s/DIV)
FIGURE 17. STEADY STATE OPERATION WITH FULL LOAD, (5s/DIV)
LX 2V/DIV VOUT RIPPLE 50mV/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 0.5A/DIV FIGURE 19. MODE TRANSITION DCM TO CCM, (50s/DIV) FIGURE 20. LOAD TRANSIENT (PWM), (50s/DIV)
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ISL8012 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5H, C1 = 2x10F, C2 = 2x10F, IOUT = 0A to 2A). (Continued)
LX 2V/DIV EN 5V/DIV VOUT 0.5V/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 0.5A/DIV
PG 5V/DIV FIGURE 21. LOAD TRANSIENT (PFM), (500s/DIV) FIGURE 22. SOFT-START WITH NO LOAD (PWM), (500s/DIV)
EN 2V/DIV VOUT 0.5V/DIV
EN 2V/DIV VOUT 0.5V/DIV
IL 0.5A/DIV
IL 0.5A/DIV
PG 5V/DIV FIGURE 23. SOFT-START AT NO LOAD (PFM), (500s/DIV)
PG 5V/DIV FIGURE 24. SOFT-START WITH PRE-BIASED 1V, (500s/DIV)
EN 2V/DIV VOUT 0.5V/DIV
EN 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV FIGURE 25. SOFT-START AT FULL LOAD, (2ms/DIV) FIGURE 26. SOFT-DISCHARGE SHUTDOWN, (2ms/DIV)
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ISL8012 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5H, C1 = 2x10F, C2 = 2x10F, IOUT = 0A to 2A). (Continued)
RSI 2V/DIV
RSI 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
PG 2V/DIV
PG 2V/DIV
FIGURE 27. RSI RESET, (200s/DIV)
FIGURE 28. RSI RESET (ZOOM OUT), (200s/DIV)
PHASE 2V/DIV
LX 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
VOUT 0.5V/DIV
IL 2A/DIV
PG 5V/DIV FIGURE 29. OUTPUT SHORT CIRCUIT, (500s/DIV)
PG 5V/DIV FIGURE 30. OUTPUT SHORT CIRCUIT RECOVERY, (500s/DIV)
3.2 OUTPUT CURRENT LIMIT (A) 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 -50 -25 0 25 50 75 100 3.3VIN 5.5VIN
TEMPERATURE (C)
FIGURE 31. OUTPUT CURRENT LIMIT vs TEMPERATURE
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ISL8012 Theory of Operation
The ISL8012 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1MHz fixed switching frequency under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency (unless forced to the fixed frequency) to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 40A. The supply current is typically only 0.1A when the regulator is shut down. signal to a current output. The voltage loop is internally compensated with the 27pF and 390k RC network. The maximum EAMP voltage output is precisely clamped to 1.47V.
VEAMP VCSA DUTY CYCLE IL
PWM Control Scheme
Pulling the MODE pin LOW (<0.4V) forces the converter into PWM mode, regardless of output current. The ISL8012 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 2 shows the block diagram. The current loop consists of the oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The gain for the current sensing circuit is typically 285mV/A. The control reference for the current loops comes from the error amplifier's (EAMP) output. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp-up. When the sum of the current amplifier CSA and the slope compensation (675mV/s) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and turn on the N-Channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 32 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier's CSA output. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error
VOUT
FIGURE 32. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the MODE pin HIGH (>1.4V) forces the converter into PFM mode. The ISL8012 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 33 illustrates the skip-mode operation. A zero-cross sensing circuit shown in Figure 2 monitors the N-MOSFET current for zero crossing. When 8 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. During the 8 detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 2. Each pulse cycle is still synchronized by the PWM clock. The PMOSFET is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak Skip current limit value. Then the inductor current is discharging to zero Ampere and stays at zero. The internal clock is disabled. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the rising edge of the internal clock as it repeats the previous operations.
CLOCK 8 CYCLES IL 0 NOMINAL +1.5% VOUT NOMINAL SKIP CURRENT LIMIT LOAD CURRENT
FIGURE 33. SKIP MODE OPERATION WAVEFORMS
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ISL8012
The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage.
UVLO
When the input voltage is below the undervoltage lock-out (UVLO) threshold, the regulator is disabled.
Mode Control
The ISL8012 has a MODE pin that controls the operation mode. When the MODE pin is driven to low or shorted to ground, the regulator operates in a forced PWM mode. The forced PWM mode remains the fixed PWM frequency at light load instead of entering the skip mode.
Soft Start-Up
The soft-start-up reduces the in-rush current during the start-up. The soft-start block outputs a ramp reference to the input of the error amplifier. This voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. When VFB is less than 0.2V at the beginning of the soft-start, the switching frequency is reduced to 1/3 of the nominal value so that the output can start up smoothly at light load condition. During soft-start, the IC operates in the SKIP mode to support pre-biased output condition.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 2. The current sensing circuit has a gain of 285mV/A, from the P-MOSFET current to the CSA output. When the CSA output reaches 1V, which is equivalent to 2.9A for the switch current (0.15V offset), the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle.
Enable
The enable (EN) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft-start-up begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100 switch.
Short-Circuit Protection
The short-circuit protection SCP comparator monitors the VFB pin voltage for output short-circuit protection. When the VFB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to minimum value to reduce the power dissipation. This comparator is effective during start-up or an output short-circuit event.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The ON-resistance for the P-MOSFET is typically 120m and the ON-resistance for the N-MOSFET is typically 110m.
RSI/PG Function
When powering up, the open-collector Power-Good output holds low for about 1ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, PG goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected. Please refer to the timing diagram in Figure 34. When the function is not used, connect RSI to ground and leave the pull-up resister R4 open at the PG pin. The PG output also serves as a 1ms delayed Power-Good signal when the pull-up resister R1 is installed. The RSI pin needs to be directly (or indirectly through a resistor) connected to Ground for PG to be actively monitoring the output voltage.
100% Duty Cycle
The ISL8012 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL8012 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET.
Thermal Shut-Down
The ISL8012 has built-in thermal protection. When the internal temperature reaches +140C, the regulator is completely shut down. As the temperature drops to +115C, the ISL8012 resumes operation by stepping through the soft-start.
Applications Information
VO RSI 1ms PG MIN 25ns 1ms
Output Inductor and Capacitor Selection
To consider steady state and transient operations, ISL8012 typically uses a 2.2H output inductor. The higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value
FIGURE 34. RSI AND PG TIMING DIAGRAM
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ISL8012
can be increased. It is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed as shown in Equation 1:
VO V O * 1 - --------- V IN I = -------------------------------------L * fS (EQ. 1)
Output Voltage Selection
The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to Figure 1. The output voltage programming resistor, R3, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 10k and 100k, as shown in Equation 2.
R 2 x 0.8V R 3 = ---------------------------------V OUT - 0.8V (EQ. 2)
The inductor's saturation current rating needs to be at least larger than the peak current. The ISL8012 protects the typical peak current 6A. The saturation current needs be over 7A for maximum output current application. ISL8012 uses internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended X5R or X7R minimum output capacitor values are shown in Table 1.
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT VOUT (V) 0.8 1.2 1.5 1.8 2.5 3.3 3.6 COUT 22F 22F 22F 22F 22F 22F 22F L 1.5H~3.3H 1.5H~3.3H 1.8H~3.3H 2.2H~3.3H 2.2H~4.7H 2.2H~4.7H 2.2H~4.7H
If the output voltage desired is 0.8V, then R3 is left unpopulated and R2 is shorted. For better performance, add 220pF in parallel with R2 (124k).
Input Capacitor Selection
The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current from flowing back to the battery rail. One 22F X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection.
Layout Recommendation
The layout is a very important converter design step to make sure the designed converter works well. For ISL8012 buck converter, the power loop is composed of the output inductor L, the output capacitor COUT, LX pin and SGND pin. It is necessary to make the power loop as small as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal epad is preferable. In addition, a solid ground plane on the second layer is helpful for EMI performance. Then connect the epad to the ground plane with at lease 5 vias for best thermal performance.
In Table 1, the minimum output capacitor value is given for the different output voltage to make sure that the whole converter system is stable.
14
FN6616.0 March 11, 2008
ISL8012 Dual Flat No-Lead Plastic Package (DFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.85 -
NOMINAL 0.90 0.20 REF
MAX 0.95 0.05
NOTES -
A1 A3 b D
6 INDEX AREA TOP VIEW B
0.20
0.25 3.00 BSC
0.30
5, 8 -
D2
// 0.10 C 0.08 C
2.33
2.38 3.00 BSC
2.43
7, 8 -
E E2 e k L 0.20 0.35 1.59
A C SEATING PLANE SIDE VIEW A3
1.64 0.50 BSC 0.40 10 5
1.69
7, 8 -
0.45
8 2 3 Rev. 1 4/06
D2 (DATUM B) 1 2 D2/2
7
8
N Nd NOTES:
NX k E2
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
E2/2 NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6616.0 March 11, 2008

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